Conventionally, in MOS (metal-oxide semiconductor) semiconductor device manufacturing methods, there has been employed a process of forming two kinds of gate insulating films having different thicknesses in a single chip. For example, in semiconductor devices in 65 nm design rule generation, a high speed MOSFET (FET: field-effect transistor) including a thin gate insulating film having a thickness of approximately 2.2 nm is provided in an internal circuit operated at 1.2 V while an input/output MOSFET including a thick gate insulating film having a thickness of approximately 7.5 nm is provided in an input/output circuit operated at 3.3 V.
Currently, there are being examined a semiconductor device in which a low leakage MOSFET that lays weight on a function as a memory cell transistor of a DRAM (dynamic random-access memory) is formed together with the high speed MOSFET and the input/output MOSFET in a single chip. Wherein, the gate insulating film of the low leakage MOSFET has a thickness larger than the gate insulating film of the high speed MOSFET and smaller than the gate insulating film of the input/output MOSFET. Accordingly, a method for manufacturing a semiconductor device having three kinds of gate insulating films having different thicknesses in a single chip is demanded. For forming the three kinds of gate insulating films on a single substrate, a semiconductor device manufacturing method in which thermal oxidation is performed three times has been proposed (see Patent Document 1).
FIG. 11A to FIG. 11D, FIG. 12A to FIG. 12C, and FIG. 13A to FIG. 13C are sectional views showing respective steps of a conventional semiconductor device manufacturing method, specifically, a method of manufacturing a conventional MOS semiconductor device including three kinds of gate insulating films.
As shown in FIG. 11A, after forming in a silicon substrate 20 trench isolation regions 19 for separating an input/output MOSFET active region, a low leakage MSFET active region, and a high speed MOSFET active region, the silicon substrate 20 including the active regions is subjected to thermal treatment (protective oxidation) in an oxidation atmosphere. This thermal treatment forms, as shown in FIG. 11B, protective oxide films 21 each having a thickness of approximately 10 nm are formed on the input/output MOSFET active region, the low leakage MOSFET active region, and the high speed MOSFET active region. Then, the respective active regions are subjected to ion implantation for well formation, the low leakage MOSFET active region is subjected to ion implantation for channel formation with the use of a resist pattern 50 that covers the input/output MOSFEET active region and the high speed MOSFET active region as a mask, as shown in FIG. 11C, and then, the resist pattern 50 is removed. FIG. 11C shows a state in which a region 51 to be a channel (hereinafter referred to as a channel region) is formed in the low leakage MOSFET active region. Similarly, ion implantation for channel formation is performed on the input/output MOSFET and on the high speed MOSFET active region with the use of respective resist patterns (not shown) that cover respective predetermined regions, and the respective resist patterns are removed. Subsequently, as shown in FIG. 11D, the protective oxide films 21 on the respective active regions are removed by wet etching (first wet etching) using a solution containing hydrofluoric acid. FIG. 11D shows a state in which channel regions 52, 53 are formed in the high speed MOSFET active region and the input/output MOSFET active region, respectively, in addition to the channel region 51 in the low leakage MOSFET active region.
Next, the silicon substrate 20 including the input/output MOSFET active region, the low leakage MOSFET active region, and the high speed MOSFET active region is subjected to thermal treatment (first gate oxidation) in an oxidation atmosphere. This thermal treatment forms, as shown in FIG. 12A, a first gate oxide films 22 having a thickness of approximately 6.5 nm is formed on each of the input/output MOSFET active region, the low leakage MOFSET active region, and the high speed MOSFET active region.
Subsequently, as shown in FIG. 12B, after forming a resist pattern 23 that covers the input/output MOSFET active region and the high speed MOSFET active region, the first gate oxide film 22 on the low leakage MOSFET active region is removed by wet etching (second wet etching) using a solution containing hydrofluoric acid with the use of the resist pattern 23 as a mask, thereby exposing the surface of the silicon substrate 20 in the low leakage MOSFET active region.
Thereafter, as shown in FIG. 12C, after removing the resist pattern 23, the silicon substrate 20 is subjected to thermal treatment (second gate oxidation) in an oxidation atmosphere. This thermal treatment forms a second gate oxide film 24 having a thickness of approximately 5.5 nm on the low leakage MOSFET active region. In this state, each first gate oxide film 22 on the input/output MOSFET active region and the high speed MOSFET active region has a thickness of approximately 7.5 nm.
Next, as shown in FIG. 13A, after forming a resist pattern 25 that covers the input/output MOSFET active region and the low leakage MOSFET active region, the first gate oxide firm 22 on the high speed MOSFET active region is removed by wet etching (third wet etching) using a solution containing hydrofluoric acid, thereby exposing the surface of the silicon substrate 20 in the high speed MOSFET active region.
Subsequently, as shown in FIG. 13B, after removing the resist patterns 25, the silicon substrate 20 is subjected to thermal treatment (third gate oxidation) in an oxidation atmosphere. This thermal treatment forms a third gate oxide film 26 having a thickness of approximately 2 nm on the high speed MOSFET active region. In this state, the film thickness of the first gate oxide film 22 on the input/output MOSFET active region and that of the second gate oxide film 24 on the low leakage MOSFET active region vary little.
Thereafter, gate electrodes, source/drain electrodes, an interlayer insulating, a metal wiring, and the like are formed by respective known techniques to complete the method of manufacturing a semiconductor device including MOSFETs with three kinds of gate insulating films having different thicknesses. Specifically, for example, as shown in FIG. 13C, gate electrodes 54, 57, 60 are formed on the high speed MOSFET active region, the low leakage MOSFET active region, and the input/output MOSFET active region, respectively, source/drain regions 55, 58, 61 are formed on the respective sides of the respective gate electrodes 54, 57, 60 in the respective active regions, and insulating sidewalls 56, 59, 62 are formed at the respective sides of the respective gate electrodes 54, 57, 60.
Patent Document 1: Japanese Patent Application Laid Open Publication No. 2002-343879A
Patent Document 2: Japanese Patent Application Laid Open Publication No. 2003-203988A